Intel, a powerhouse in the world of semiconductor technology, is poised to turn the chipmaking industry on its head with an innovative breakthrough called PowerVia. This revolutionary approach to powering chips required a complete reimagining of both chip manufacturing and testing processes.
Traditionally, computer chips have been constructed in a layered manner, akin to building a pizza from the bottom up. You start with the smallest components, the transistors, and then stack up layers of progressively larger wires, including power connections. However, this conventional method has encountered mounting issues as chips have become smaller and denser, resulting in a tangled web of interconnects and power connections that hinder chip performance.
Power and signal degradation have become significant concerns, necessitating workarounds or simply increasing power input. Ben Sell, Vice President of Technology Development at Intel, highlights the magnitude of this shift, stating that what were once afterthoughts, power and signal delivery, are now paramount in chip design.
Intel, along with other leading-edge chipmakers, sought a solution termed “backside power.” This approach aims to reroute power wires to the underside or “back” of the chip, leaving the front side primarily for interconnection purposes.
Intel’s solution, known as PowerVia, represents a significant departure from conventional chipmaking. Two new research papers set to be published at the 2023 VLSI Symposium showcase how Intel has not only devised a method to manufacture PowerVia but has also successfully tested it, yielding exceptional performance results.
The manufacturing process is a noteworthy aspect of this breakthrough. Instead of the traditional bottom-up approach, transistors are constructed first, followed by interconnect layers. The innovation occurs when the wafer is flipped over and meticulously polished to expose the bottom layer to which power wires are connected. This method, termed “silicon technology,” leaves behind only a minuscule amount of silicon on the wafers.
The benefits of PowerVia are numerous and far-reaching, outweighing the added complexity of this novel process. For example, power wires can occupy up to 20% of the front-side real estate in conventional chips. By eliminating them, interconnect layers can be simplified and optimized, offsetting the costs associated with this groundbreaking process.
Moreover, the advantages extend to chip performance. PowerVia improves both power delivery and signal wiring, resulting in more efficient speed, reduced power consumption, and improved performance—a realization of Moore’s Law.
The test chip, named Blue Sky Creek, demonstrated significant performance improvements. It showcased a >5% frequency boost and >90% cell density with acceptable debug times compared to Intel 4, marking a substantial leap in performance by merely reconfiguring wiring.
Innovative debugging techniques had to be developed, given that transistors are now sandwiched in the middle of the chip. This necessitated the development of new debug capabilities and the intentional introduction of errors into the chip to test and verify these capabilities.
Intel’s approach to developing PowerVia involved creating a special test process node with the power and interconnect design planned for Intel 20A. This unique approach allowed Intel to verify the viability of PowerVia without introducing unexpected issues.
PowerVia’s introduction in Intel-manufactured silicon is slated to begin with the Intel 20A node in 2024. This innovation marks a significant advancement in chipmaking technology, placing Intel and its customers ahead of competitors by approximately two years in terms of backside power.
Intel’s PowerVia represents a major leap forward in chipmaking, promising more efficient, faster, and less power-hungry devices. The technology is set to debut in Intel’s Arrow Lake processor, built using the Intel 20A process, offering billions of inverted transistors that work more efficiently than ever before.